Diode chain with guard-band

ABSTRACT

The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.

CROSS-REFERENCES

This application is a continuation-in-part of application Ser. No.12/188,376, filed Aug. 8, 2008, which claims the benefit of U.S.Provisional Application Ser. No. 60/954,655 filed Aug. 8, 2007,entitled, “Improved Diode Chain with N Guard-ring”, the entire contentof which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to an electrostatic discharge (ESD)protection circuit. More specifically, the present invention relates toan improved ESD circuit having a chain of diodes with a guard-band.

BACKGROUND OF THE INVENTION

During an ESD event, large currents can flow through an IntegratedCircuit (IC), potentially causing damage to the IC. To avoid thisdamage, ESD protection circuits are added. In many ESD protectioncircuits, a chain of diodes is used. However, during very fast ESDevents, a voltage overshoot is associated with every diode. When placingN diodes in series, this total overshoot is very high during the ESDevent, which creates latch-up (dead short circuit between Vdd andground), thus degrading or damaging sensitive nodes (e.g. gate oxides)in the circuitry.

A well-known approach to prevent latch up is to surround the diode(s)with a guard-band, which is, in the case of a P-substrate process, aheavily P-doped region. This will cause the current that is injected inthe substrate to flow safely to the guard-band, which is generallyconnected to the ground. Thus, the guard-band isolates the diode fromthe outside circuitry. However, the P+ guard-band causes the triggeringof the diode, and/or the diode chain to slow down.

Thus, there is a need in the art for a solution to provide an improvedESD protection device, which prevents any damage to the circuitry andalso provides for an improved fast triggering during the ESD event.

SUMMARY OF THE INVENTION

The embodiments of the present invention provides an ESD protectiondevice comprising at least one diode in a first well of firstconductivity type formed on a second well of a second conductivity type.The device further comprises a guard-band of the first conductivity typesurrounding at least a portion of said at least one diode.

In one embodiment of the present invention, the first conductivity typecomprises an N-type doping region and the second conductivity typecomprises a P-type doping region.

In another embodiment of the present invention, the first conductivitytype comprises a P-type doping region and the second conductivity typecomprises an N-type doping region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a top view of an ESD device in accordance with a oneembodiment of the present invention.

FIG. 1B illustrates a cross-section view along line 1B of the ESD deviceof FIG. 1A.

FIG. 2 illustrates a top view of an ESD device in accordance with analternate embodiment with reference to FIG. 1A of the present invention.

FIG. 3A illustrates a top view of an ESD device in accordance withanother embodiment of the present invention.

FIG. 3B illustrates a top view of an ESD device circuit in accordancewith an alternate embodiment with reference to FIG. 3A of the presentinvention.

FIG. 3C illustrates a cross-section view of an ESD device circuit inaccordance with an alternate embodiment of the present invention withreference to FIGS. 3A and 3B.

FIG. 4 illustrates a top view of the ESD device of FIG. 2 and a triggercircuit in accordance with yet another embodiment of the presentinvention.

FIG. 5A illustrates a measured data plot of a current and voltage curveof prior art and of the present invention.

FIG. 5B illustrates a measured data plot of an overshoot voltage andcurrent of prior art and of the present invention.

FIG. 6 illustrates a top view of an embodiment of an ESD devicecomprising multiple guard-bands.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides an ESD protection device having a diodechain, which is further optimized for fast triggering. According to theembodiments of the present invention, this is achieved by replacing theP+ guard-band around the diodes by an N-type guard-band to form an NPNtransistor. The NPN transistor is a faster device compared to the PNPtransistor. This is due to the fact that the conduction of the PNP iscontrolled by holes and the conduction of the NPN by electrons. Sincethe mobility of electrons is larger than the mobility of holes, the NPNstructure will trigger faster than the PNP structure.

In one embodiment of the present invention, FIG. 1A illustrates a topview of an ESD protection device 100 and FIG. 1B illustrates across-section of the ESD device 100 taken along line 1B in FIG. 1A. TheESD device 100 includes a chain of three diodes 102 formed on asubstrate 104 of a material of a first conductivity type, preferably aP-type doping region (P-sub). Each of the diodes 102 contains an N dopedand P doped region As shown in FIGS. 1A and 1B, a well 106 of a secondconductivity type, preferably an N-type doping region (N-well) is formedin the P-sub 104. Both N-well 106 and P-sub 104 may includesemi-conducting material, such as, for example, silicon, germanium orcombinations of both. P-sub 104, as shown in FIG. 1A, may preferably beelectrically grounded. Each of the PN diodes 102 also include a PNP 103transistor formed by the PN junction of the diode 102 and the P-sub 104as second P junction as illustrated in FIG. 1B. Even though in thisembodiment of the present invention, the first conductivity type isdefined as a P-type doping region and the second conductivity type isdefined as an N-type doping region, one skilled in the art wouldappreciate that the first conductivity type may be the N-type dopingregion and the second conductivity type may be the P-type doping region.

In order to reduce the leakage current, a guard-band structure is formedon the active area. Generally in the prior art, a heavily doped P+region is formed as a guard-band on the active area. This is because theP+ region has the same doping type as the substrate, P-sub 104. Thismakes a low ohmic connection between the P+ and the substrate region.However, a high ohmic is needed for the guard-band to the ground (i.e.the substrate). Therefore, in the present invention, an N+ guard-band108 is formed on each side of the diodes 102 as illustrated in FIGS. 1Aand 1B. This in turn creates an NPN transistor 105 formed between adiode cathode (N+ in diode 102), P-sub 104 and the N+ guard-band 108.The PNP 103 will initiate a trigger mechanism by providing an ESDcurrent to the NPN 105 to turn on the NPN 105, which in turn will alsoflow current back to the PNP 103. In this manner, both the PNP 103 andthe NPN 105 function together to initiate a fast triggering of thediodes during an ESD event. So, by changing the guard-band type to N+,the PNP 103 is strengthened by an NPN 105 and this combination of thetwo bipolar transistors 103 and 105 optimize the diode chain triggeringbehavior.

Additionally, although not shown, each of the N+ guard-bands 108 may beconnected to ground or to a lower potential voltage. Alternatively, oneor more of the N+ guard-bands 108 may be connected to ground and therest of them may be connected to a lower potential voltage. The lowerpotential voltage as defined in this embodiment is any voltage lowerthan the voltage of the anode of the diode structure (P+ in 102). Thelower potential voltage may include a voltage outside the ESD circuit100 or the voltage one of the cathodes (N+ in 102) of the diode 102 inthe ESD circuit 100. For example, in FIGS. 1A and 1B, the N+ guard-band108 may be connected to ground or other lower potential outside thedevice 100, the N+ guard-band 108′ maybe connected to N+ of diode 102′,the N+ guard-band 108″ may be connected to N+ of diode 102″ and the N+guard-band 108′″ may be connected to N+ of diode 102′″.

In an alternate embodiment of the present invention, N+ guard-band 108is formed on all sides of each of the diodes 102 as illustrated in topview of an ESD device 200 of FIG. 2. In this embodiment, the top andbottom structure of the diodes 102 also include N+ guard-band 108, thuscompletely enclosing the diodes 102. This creates a largerperimeter/area for the N+ guard-band 108, which provides for an evenstronger NPN 105 formed for each of the diodes 102 in the device, thusgenerating a stronger and faster diode chain triggering behavior.Furthermore, in this embodiment, the N+ tap in the diode 102 iscompletely surrounded by a P+ tap. However, one skilled in the art wouldappreciate that this is only meant to illustrate a different diodelayout and that the invention is not limited to any particular diodeconfiguration.

Even though the diodes 102 illustrated in FIGS. 1 and 2 are StandardTrench Isolation (STI) type diodes, it is obvious to one skilled in theart that the diodes 102 may include other types such as gated diode,NO-STI diodes, etc. Also, in both FIGS. 1 and 2, three diodes areillustrated to be placed in series, however, it is obvious to oneskilled in the art that the invention is not limited to this number, andis applicable to any number of diodes. In fact, only one diode maypreferably be implemented to function according to an alternateembodiment of the present invention.

Although, FIGS. 1 and 2 illustrate only two types of configurations ofthe guard-band, it is known to one skilled in the art that other typesof configurations can also be formed. Also, in both FIGS. 1 and 2, aguard-band 108 of N+ doping is used, however, one skilled in the artwould understand that the invention is not limited to this doping typeand other doping types may be used. One such example is to replace theP-substrate 106 with an N-substrate (not shown). In this example, N-well106 will be replaced by P-well (not shown), each of the N+ guard-bands108 will be replaced by P+ (not shown), P+ taps in each of the diodes102 will be replaced by N+ taps (not shown) and the N+ tap in each ofthe diodes 102 will be replaced by P+ taps (not shown). In this example,an NPN transistor would be formed by the PN junction diode and the andthe N-substrate. A PNP is added by the added P+ guard-band, theN-substrate and the P-well. Also, in this example, the P+ guard-bandwould be coupled to a higher potential voltage. The higher potentialvoltage in this example would be any voltage higher than the voltage ofthe cathode of the diode and, thus, the P+ guard-band would preferablybe coupled to the anode of the diode.

Furthermore, in the embodiment illustrated in FIGS. 1 and 2, P+ taps ofthe diodes 102 are placed at the outside and the N+ tap is placedbetween the P+ taps, however, one skilled in the art knows the inventionis not limited to this particular order and shape of placing the P+ andN+ taps of the diodes.

The embodiments of FIGS. 1 and 2 of the present invention are shown onlyfor N-well diodes. However, anyone skilled in the art can understandthat a similar effect can be obtained for a chain of P-well diodes asshown in FIGS. 3A and 3C of the present invention. FIG. 3A illustrates atop view of an ESD device 300 in another embodiment of the presentinvention. FIG. 3C illustrates a cross-section view of an alternativeESD device. The ESD device 300 includes a chain of three P-well diodes302 enclosed by an N-well 303 which are formed on a substrate of p-typematerial (P-sub) 104. Each of the diodes 102 contains an N doped and Pdoped region. In this embodiment, an isolated P-well, 306 is placed inthe N-well 303 around the P-well diodes 302 as shown in FIGS. 3A and 3C.The P-well diodes 302 lie directly in the P-well 306 and the deep N-welllayer 303 lies underneath the P-well 306 to isolate it from theP-substrate 304. So, in this embodiment, the N-well 303 functions as aguard-band, thus forming an NPN transistor 305 between the diode cathode(N+ in diode 302), the isolated P-well 306 and the N-well 303.

In an alternate embodiment, a P+ region 308 is added in the N-well 303between the P-well diodes 302 of the device 300 of FIG. 3A asillustrated in FIG. 3B. FIG. 3B illustrates a top view of the device 300of FIG. 3A with the added P region 308. By adding the P+ region 308 inthe deep N-well 303 between the P-well diodes 302 would form a PNPtransistor 307 as shown in FIGS. 3B and 3C. This PNP transistor 307would add a PNP pumping effect to the already existing NPN 305 betweenthe diodes 302, thus further strengthening the NPN 305. This behavior ofthe combination of the NPN and the PNP is the same as described abovewith respect to FIGS. 1A and 1B. Note that in this embodiment, the deepN-well 303 can be biased to any given potential. This is typically doneby adding N+ in the deep N-well 303 to make contact between the powerlines and the N-well 303. The N-well and deep N-well are placed aroundthe diode to clearly isolate the P-well to the substrate. Generally, theN-well is mostly connected to a fixed voltage source, i.e. one of thepower lines, however, the N-well can also be connected to other nodes oreven remain floating.

FIG. 4 illustrates an ESD protection device 400 in accordance with yetanother embodiment of the present invention. In this embodiment, the N+guard-band 108 of the ESD device 200 is connected to a triggeringcircuit 402 as shown in FIG. 4. The triggering circuit 402 functions tospeed up the diode chain as will be described in greater detail below.

In the example illustrated in FIG. 4, the trigger circuit 402 includes aresistor 404, a capacitor 406 and an inverter 408. The capacitor 404 ofthe circuit 402 will pull during ESD, causing the input of the inverter408 to be high. The output of the inverter 408 will switch to low whichin turn will produce a low potential to the N+ guard-band 108. This willhelp to turn on the PNP 103 (since PN junction is forward-biased) whichin turn supplies current to turn on the NPN 105. During normal operationthe capacitor 404 will pull the input of the inverter 408 to ground. Theoutput of the inverter 208 will then turn to high. This will pull the N+guard-band 108 to the high potential, keeping the PN junction betweensubstrate and guard-band 108 in reverse, which will turn off the NPN105. This will prevent the NPN 105 from conducting any current (i.e. NPNremains turned off), which in turn prevents the PNP 103 from conductingany current during normal operation. Thus, the trigger circuit 402 usesthe RC to bias the N+ guard-band 108 low during ESD and high duringnormal operation. During normal operation the NPN will create an extraleakage path, by pulling the emitter high during normal operation, theNPN is disabled, and will introduce less leakage during normaloperation. With this circuit a clear difference can be made betweennormal operation and operation when ESD occurs. The triggering circuit402 in this embodiment is the RC transient detector, however, oneskilled in the art would appreciate that the triggering circuit canconsist of other elements such as diodes, inductances, transistors etc.,including a combination of these elements. The N+ guard-band 108 in thedevice 400 can also be shorted to ground or to any reference voltage inthe IC.

Referring to FIG. 5A, there is illustrated a graphical plot of datameasurements of current (I) and voltage (V) of the ESD circuits of priorart and the present invention. The x-axis represents the voltage (V) andthe y-axis represents the current (I). The data measurements are takenfor a very short time period, preferably in the range of 2-3nano-seconds. The data measurements illustrate a voltage curve 502 ofthe prior art ESD device with a P+ guard-band, a voltage curve 504 ofthe N+ guard-band 108 of the ESD device 200 of FIG. 2 and a voltagecurve 506 of the N+ guard-band 108 of the ESD device 100 of FIG. 1. Asillustrated in FIG. 5A, for the same amount of current, the voltages 504and 506 of the N+ guard-band 108 of the ESD devices 200 and 100respectively are much lower compared to the voltage 502 of the ESDdevice of the prior art with a P+ guard-band. In fact, the voltage 506of the N+ guard-band 108 of the ESD device 200 is even lower than thevoltage 504 of the N+—guard-band of the ESD device 100. As discussedabove, this is due to the fact that the N+ guard-band 108 of FIG. 2creates a larger perimeter/area around the diodes, thus providing for aneven stronger NPN formed for each diode in the device

Referring to FIG. 5B, there is illustrated a graphical plot of datameasurements of overshoot voltage (x-axis) vs. the current (y-axis) ofthe ESD circuits of the prior art and the present invention. The datameasurements of the overshoot voltage (i.e. maximum voltage of the ESDdevice) are taken for an even shorter time period, preferablyapproximately 100 pico-seconds. The data measurements illustrate anovershoot voltage curve 502′ of the prior art ESD device with a P+guard-band, an overshoot voltage curve 504′ of the N+ guard-band 108 ofthe ESD device 200 of FIG. 2 and an overshoot voltage curve 506′ of theN+ guard-band 108 of the ESD device 100 of FIG. 1. As illustrated inFIG. 5B, for the same amount of current, the overshoot voltages 504′ and506′ of the N+ guard-band 108 of the ESD devices 200 and 100respectively are much lower compared to the overshoot voltage 502′ ofprior art ESD device with the P+ guard-band. In fact, the overshootvoltage 506′ of the N+ guard-band 108 of the ED device is even lowerthan the overshoot voltage 504′ of the N+-guard-band 108 of the ESDdevice 100. As discussed above, this is due to the fact that the N+guard-band 108 of FIG. 2 creates a larger perimeter/area around thediodes, thus providing for an even stronger NPN formed for each diode inthe device.

In FIG. 6 yet another embodiment is shown. Three diodes 602′, 602″ and602′″ are shown. It should be noted that any series of at least onediode can be drawn according to the principle of the invention. Betweenthe diodes, guard-bands 608, 609, 608 a′, 609′, 608 b′, 608 a″, 609″,608 b″, 608′, and 609′″ are placed. The guard-bands can be coupled todifferent nodes: for example, guard-bands 609, 609′, 609″, 609′″ can becoupled to a first potential and guard-bands 608, 608 a′, 608 b′, 608a″, 608 b″, and 608′″ can be coupled to a second potential. In oneembodiment, the first potential is a higher potential than the secondpotential. In another embodiment, the second potential is a higherpotential than the first potential. In another embodiment, the firstpotential is a high potential such has Vdd and the second potential is alow potential such as ground or Vss. In yet another embodiment, thefirst potential is a low potential such as ground or Vss and the secondpotential is a high potential such as Vdd. Alternatively, theguard-bands can all be coupled to the same node, each guard-band couldbe coupled to a different node, or various combinations of guard-bandscould be coupled to various different nodes.

For the exemplary case where guard-bands 609, 609′, 609″, 609′″ arecoupled to a first potential and guard-bands 608, 608 a′, 608 b′, 608a″, 608 b″, and 608′″ are coupled to a second potential, a first groupof NPNs is formed comprising any of the diode N-wells 606′, 606″ and606′″ as the collector, P-well 604 as the base and at least one of theguard-bands 608, 608 a′, 608 b′, 608 a″, 608 b″ and 608′″ as theemitter. A second group of NPNs is formed comprising any of theguard-bands 609, 609′, 609″, and 609′″ as the collector, P-well 604 asbase and at least one of the diode N-wells 606′, 606″ and 606′″ as theemitter. A third group of NPNs is formed comprising any of theguard-bands 609, 609′, 609″, and 609′″ guard-bands as the collector,P-well 604 as the base, and at least one of the guard-bands 608, 608 a′,608 b′, 608 a″, 608 b″ and 608′″ as the emitter.

Note that although the guard-bands in FIG. 6 are bordering on two sidesof each diode, one embodiment of the invention might include guard-bandsto be added to border on only one side, on three sides, or on all sides.Also note that the relative geometries of the guard-bands, diodes, andwells are drawn in an exemplary fashion only. One should recognize thatother relative geometries may be formed. Furthermore, while theguard-bands, diodes, and wells are drawn uniformly, different dimensionsmay also be used.

In FIG. 6, three guard-bands are 608 a′, 609′ and 608 b′ are placedbetween diodes 606′ and 606″. Also, guard-bands 608 a″, 609″, 608 b″ areplaced between diodes 606″ and 606′″. Though three guard-bands are shownbetween the diodes, any number of guard-bands can be placed. Each of theguard-bands can be coupled to a different, or the same referencepotential. Likewise, on the left side of diode 606′ two guard-bands 609and 608 are placed. On the right side of diode 606′″ two guard-bands608′″ and 609′″ are placed. According to the principle of the invention,any number of guard-bands can be placed, each of the guard-bands can becoupled to the same or to a different reference potential.

In one embodiment, in order to strengthen the third group of NPNs, thesurface area between pairs of adjacent guard-bands, such as 609 and 608,608 a′ and 609′, 609′ and 608 b′, 608 a″ and 609″, 609″ and 608 b″, and608′″ and 609′″ may be devoid of isolation such as STI by adding a polygate. The poly gate may be coupled to a low reference potential such asground to avoid adding leakage.

One should also note that though FIG. 6 depicts the guard-bands asN-type formed in a P-well, in another embodiment the conductivity typesof the wells may be switched such that the guard-bands may be P-typeformed in an N-well. Likewise, in such an embodiment, the diode wellsmay switch conductivity.

Thus, as described in the embodiments of the present invention above, anN+ guard-band around the diodes provides for a much reduced voltageincluding the overshoot voltage in the ESD protection devices, thuspreventing damage to the circuitry during an ESD event. It is noted thatsimilar results may be achieved by a Silicon Controlled Rectifier (SCR)in a larger time domain (after the settling time), however, an SCR wouldnot function as fast and trigger as quickly as the NPN transistor formedby placing an N+ guard-band around the diodes as described above. Also,as discussed above, the present invention could be implemented usingonly one diode; however, the one diode may not go into an SCR mode. Thevoltages where these devices operate are below the minimum voltage thatis needed to sustain the SCR in an SCR mode.

Although various embodiments that incorporate the teachings of thepresent invention have been shown and described in detail herein, thoseskilled in the art can readily devise many other varied embodiments thatstill incorporate these teachings without departing from the spirit andthe scope of the invention.

What is claimed is:
 1. An electrostatic discharge (ESD) protectiondevice comprising: at least one diode in a first well of a firstconductivity type formed directly in a second well of a secondconductivity type; a first guard-band of the first conductivity typebordering at least a portion of the at least one diode, wherein thefirst guard-band is formed completely within the second well; and asecond guard-band of the first conductivity type bordering at least aportion of the first guard-band, wherein the second guard-band is formedcompletely within the second well.
 2. The ESD protection device of claim1, wherein the first conductivity type comprises an N-type doping regionand the second conductivity type comprises a P-type doping region. 3.The ESD protection device of claim 2, wherein a PNP transistor is formedby a PN junction of the at least one diode and the second well of thesecond conductivity type.
 4. The ESD protection device of claim 3,wherein an NPN transistor is formed by the first guard-band of the firstconductivity type, the second well of the second conductivity type, andthe second guard-band of the first conductivity type.
 5. The ESDprotection device of claim 1, wherein the first conductivity typecomprises a P-type doping region and the second conductivity typecomprises an N-type doping region.
 6. The ESD protection device of claim5, wherein a PNP transistor is formed by the first guard-band of thefirst conductivity type, the second well of the second conductivitytype, and the second guard-band of the first conductivity type.
 7. TheESD protection device of claim 6, wherein an NPN transistor is formed bythe first guard-band of the first conductivity type, the second well ofthe second conductivity type, and the second guard-band of the firstconductivity type.
 8. The ESD protection device of claim 1, wherein thefirst guard-band is coupled to a cathode of the at least one diode. 9.The ESD protection device of claim 8, wherein the second guard-band iscoupled to an anode of the at least one diode.
 10. The ESD protectiondevice of claim 1 further comprising a triggering circuit connected tothe first guard-band.
 11. The ESD protection device of claim 10, whereinthe triggering circuit connects the first guard-band to a low potentialduring an ESD event.
 12. An electrostatic discharge (ESD) protectiondevice comprising: at least one diode in a first well of a firstconductivity type formed directly in a second well of a secondconductivity type; a first guard-band of the first conductivity typebordering at least a portion of the at least one diode; and a secondguard-band of the first conductivity type bordering at least a portionof the first guard-band; wherein the first conductivity type comprisesan N-type doping region and the second conductivity type comprises aP-type doping region; wherein a first NPN transistor is formed by thefirst well of the first conductivity type, the second well of the secondconductivity type and the first guard-band of the first conductivitytype, and further wherein a second NPN transistor is formed by the firstguard-band of the first conductivity type, the second well of the secondconductivity type, and the second guard-band of the first conductivitytype.
 13. The ESD protection device of claim 12, wherein the firstguard-band is coupled to a low voltage, wherein the low voltage is atleast as low as a voltage of an anode of the at least one diode.
 14. TheESD protection device of claim 13, wherein the second guard-band iscoupled to a high voltage, wherein the high voltage is at least as highas the voltage of a cathode of the at least one diode.
 15. Anelectrostatic discharge (ESD) protection device comprising: at least onediode in a first well of a first conductivity type formed directly in asecond well of a second conductivity type; a first guard-band of thefirst conductivity type bordering at least a portion of the at least onediode; and a second guard-band of the first conductivity type borderingat least a portion of the first guard-band; wherein the firstconductivity type comprises an P-type doping region and the secondconductivity type comprises a N-type doping region; wherein a first PNPtransistor is formed by the first well of the first conductivity type,the second well of the second conductivity type and the first guard-bandof the first conductivity type, and further wherein a second PNPtransistor is formed by the first guard-band of the first conductivitytype, the second well of the second conductivity type, and the secondguard-band of the first conductivity type.
 16. The ESD protection deviceof claim 15, wherein the first guard-band is coupled to a high voltage,wherein the high voltage is at least as high as the voltage of a cathodeof the at least one diode.
 17. The ESD protection device of claim 16,wherein the second guard-band is coupled to a low voltage, wherein thelow voltage is at least as low as a voltage of an anode of the at leastone diode.
 18. The ESD protection device of claim 1, wherein a surfacearea between the first guard-band and the second guard-band is devoid ofisolation.
 19. The ESD protection device of claim 1, further comprisinga gate placed over at least a portion of an area between the firstguard-band and the second guard-band.
 20. The ESD protection device ofclaim 12, wherein a surface area between the first guard-band and thesecond guard-band is devoid of isolation.
 21. The ESD protection deviceof claim 12, further comprising a gate placed over at least a portion ofan area between the first guard-band and the second guard-band.
 22. TheESD protection device of claim 15, wherein a surface area between thefirst guard-band and the second guard-band is devoid of isolation. 23.The ESD protection device of claim 15, further comprising a gate placedover at least a portion of an area between the first guard-band and thesecond guard-band.